1. Field of the Invention
The present invention relates to the structure of a semiconductor device such as an insulated gate transistor having a wiring made of an aluminum material and a method of manufacturing the semiconductor device. Also, the present invention relates to an active matrix substrate having a scanning line made of an aluminum material and a method of manufacturing the active matrix substrate.
It should be noted that the semiconductor device of the present invention includes not only elements such as a thin film transistor or a MOS transistor but also an electronic equipment having a semiconductor circuit formed of insulated gate semiconductor elements and an electronic equipment such as a personal computer or a digital camera having an electro-optic display device (representatively, a liquid crystal display device) formed of an active matrix substrate.
2. Description of the Related Art
Attention has been now paid to an active matrix liquid crystal display having a pixel matrix circuit and a drive circuit made up of a thin film transistor (hereinafter referred to as xe2x80x9cTFTxe2x80x9d) formed on an insulating substrate. There are the liquid crystal display for a projector which is about 0.5 to 2 inches in size and the liquid crystal display for a note-type personal computer which is about 10 to 20 inches in size. Thus the liquid crystal display is used as a small-sized display or a middle-sized display.
The liquid crystal display has been so developed as to increase the display area. However, an increase in the display area causes a pixel matrix circuit which forms an image display section to increase in area, with which source wirings, gate wirings and so on which are arranged in a matrix become long, to thereby increase a wiring resistance. Further, since it is necessary to thin the wirings in response to a request for fining, an increase in the wiring resistance is more actualized. Also, a TFT is connected to the source wirings and the gate wirings for each of pixels, and an increase in the number of pixels leads to a problem that a parasitic capacitance increases. In the liquid crystal display, the gate wirings and the gate electrodes are generally integrated with each other, whereby a delay of gate signals is actualized with an increased area of the panel.
Under the above-mentioned circumstance, the gate wirings are made of a material mainly containing aluminum low in specific resistance. When the gate wirings and the gate electrodes are made of the material mainly containing aluminum, a gate delay time can be shortened, and also the TFT can be operated at a high speed. In general, in the case where the gate wirings are made of the aluminum material, aluminum is coated with an anodic oxide film so as to improve the heat resistance of the wirings.
Also, up to now, an attempt has been made that the thin film transistor is brought in an offset structure or an LDD (light doped drain) structure, to thereby reduce an off-state current. In Japanese Patent Publication No. 2759415, the present applicant teaches a technique by which the thin film transistor of the LDD structure is manufactured. The above-mentioned patent publication discloses a method in which a gate electrode made of aluminum is anodically oxidized to form the LDD structure on a semiconductor layer in a self-aligning manner. This method will be described with reference to FIGS. 49A to 49F.
An under film 11 such as a silicon oxide film is formed on a glass substrate 10. A semiconductor layer 13 consisting of a polycrystal silicon film is formed on the under film 11, and a gate insulating film 14 is formed on the semiconductor layer 13. Then, an aluminum film is formed on the upper surface and patterned by using a resist mask 16 to form a gate electrode 15 made of aluminum (FIG. 49A).
The gate electrode 15 is anodically oxidized in an electrolyte to form a porous alumina film 17. An oxalic acid aqueous solution is used for the electrolyte. Because the surface of the gate electrode 15 is covered with the resist mask 16, the porous alumina film 17 is formed only on side surfaces of the gate electrode 15. In this specification, the porous alumina film 17 is mentioned as xe2x80x9cporous A.O. film 17xe2x80x9d (FIG. 49B).
After the removal of the resist mask 16, the gate electrode 15 is again anodically oxidized to form a barrier (non-porous) alumina film 18. Ethylene glycol aqueous solution containing tartaric acid of several % therein is used for an electrolyte. An aluminum pattern remaining through two anodic oxidation process functions as a gate electrode 15xe2x80x2. In this specification, the barrier alumina film 18 is mentioned as xe2x80x9cbarrier A.O. film 18xe2x80x9d (FIG. 49C).
Then, the gate insulating film 14 is patterned with the A.O. films 17 and 18 as a mask to form a gate insulating film 14xe2x80x2 (FIG. 49D).
After the removal of the porous A.O. film 17, the semiconductor layer 13 is doped with impurities that give an n-type or p-type conductivity through the plasma doping method. The doping process is implemented twice. A first doping process is conducted at a low acceleration so that the gate insulating film 14xe2x80x2 functions as a mask, and the dose amount is set to be large. A second doping process is conducted at a high acceleration so that the impurities pass through the gate insulating film 14xe2x80x2, and the dose amount is set to be small in order to form an LDD region. In the semiconductor layer 13, a channel formation region 20, a source region 21, a drain region 22 and lightly-doped impurity regions 23, 24 are formed in a self-aligning manner. The lightly-doped impurity region 24 on the drain region 22 side constitutes the LDD region. When the gate insulating film 14xe2x80x2 is allowed to function as a complete mask during the doping process, the regions 23 and 24 can be constituted as an offset region (FIG. 49E).
Subsequently, an interlayer insulating film 25 that covers the TFT is formed on the upper surface. Then, contact holes are opened in the interlayer insulating film 25, into which source and drain electrodes 26 and 27 are formed. Finally, a hydrogenation process is conducted to complete the TFT (FIG. 49F).
The application of an anodic oxidation process enables a TFT of the LDD structure or the offset structure to be formed in the self-aligning manner.
However, in order to conduct the anodic oxidation process, it is necessary to connect all of the electrodes and wirings to be anodically oxidized to a voltage supply wiring for anodic oxidation. For example, in the case where the technique disclosed in the above-mentioned Japanese Patent Publication is applied to the active matrix liquid crystal panel, it is necessary to connect all of the active matrix circuit and the gate electrode/wiring of the thin film transistor that constitutes a driver circuit to the voltage supply line. For achieving this connection, it is necessary to form the voltage supply wiring on the substrate, and a surplus space must be ensured.
Also, the structure is made so that the respective gate electrodes and the wirings are short-circuited by the voltage supply line at the time of anodic oxidation. Because the voltage supply line and the connection portions to the voltage supply line are not required after the anodic oxidation process, they are removed by etching so that the respective gate wirings and electrodes are cut off. To achieve this operation, a circuit arrangement must be designed taking a space in which the voltage supply line is formed and an etching process margin into consideration.
Accordingly, in manufacturing the transistor using the anodic oxidation process, the space in which the voltage supply line is formed and the etching margin are required, which impedes the high integration of the circuit and the reduction of the base area. In addition, since aluminum is exposed from the cut-off faces of the wirings, the heat resistance is deteriorated.
Also, in the TFT shown in FIGS. 49A to 49F, the operation defect of the TFT is confirmed even if a process temperature is 300 to 450xc2x0 C. after the formation of the aluminum wiring. Various factors of the operation defect are presumed. In particular, it is presumed that many cases in which the operation defect occurs in a top gate TFT are caused by a protrusion such as hillock or whisker occurring at the gate electrode which penetrates the gate insulating film and reaches the channel formation region, or short-circuiting between the gate electrode and the channel which is generated by diffusing aluminum atoms in the gate insulating film.
For that reason, up to now, the upper limit of the heat temperature after the aluminum wiring has been formed is limited to about 450xc2x0 C. To achieve this, in a process of activating the impurities added to the source and drain regions, it is necessary to conduct a laser activation by an excimer laser together with a thermal activation process because it is insufficient to conduct only the thermal activation process.
Also, a high mobility is demanded for the TFT at the present, and it is weightily presumed that a crystalline silicon film which is higher in mobility more than an amorphous silicon film will be used as a semiconductor layer. Up to now, in order to obtain the crystalline silicon film by a heat treatment, it is necessary to employ a quartz substrate having a high strain point. However, because the quartz substrate is expensive, crystallization at a low temperature is demanded so that an inexpensive glass substrate can be employed.
A technique by which the crystallization temperature is lowered is disclosed in Japanese Patent Application Laid-open Nos. Hei 6-232059, Hei 7-321339, and the like by the present applicant. The technique is that a slight amount of catalytic elements are introduced into an amorphous silicon film, and then a heat treatment is conducted to the film, to thereby obtain a crystallized silicon film. The catalytic elements that promote crystallization are elements selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au and Ge. The use of the above-mentioned crystallization technique makes it possible to produce a polycrystal silicon film at a process temperature which the glass substrate can withstand.
The above-mentioned crystallization technique leads to a problem in that the catalytic elements used for crystallization remain in the polycrystal silicon film, which causes the reliability of a TFT and the uniformity of the characteristics to be degraded. In view of this, in order to eliminate this problem, the present applicant discloses in Japanese Patent Application Laid-open No. Hei 8-330602 a technique by which metal elements in a polycrystal silicon film is gettered after the formation of a wiring made of an aluminum material. In the technique disclosed in the above-mentioned publication, the source and drain regions to which phosphorus is added are employed for gettering sink, and the catalytic elements in the channel formation region are gettered in the source and drain regions by a heat treatment.
However, in the case where an aluminum material that is low in heat resistance is used for the wiring, even if the wiring is coated with the anodic oxide film, a heat temperature for gettering is limited to 300 to 450xc2x0 C. Because the heat temperature of 300 to 450xc2x0 C. is low as a temperature for sufficiently gettering the metal elements in the polycrystal silicon film, a long processing period of time is required. For that reason, the diffusion of aluminum from the gate electrode and the expansion of the gate wirings due to hillock or the like are liable to occur.
As described above, it is desired to use the aluminum material for the wiring from the view point of lowering the resistance of the wirings. Since aluminum can be anodically oxidized, the thin film transistor having the LDD structure or the offset structure can be produced in a self-aligning manner by using the anodic oxidation technique. However, because it is necessary to form a voltage supply wiring for anodic oxidation, the high integration of circuits and the reduction of the substrate area are impeded.
Also, even if aluminum is coated with an anodic oxide, the process temperature after the formation of the gate wiring is limited to about 400xc2x0 C. Also, aluminum diffuses from the gate wiring, the gate wiring and the channel are short-circuited due to the occurrence of hillock, or the gate wiring is deformed, resulting in the operation defect of the TFT.
The present invention has been made in order to eliminate the above-mentioned problems with the prior art, and therefore an object of the present invention is to enable an aluminum material to be anodically oxidized without forming a voltage supply wiring for anodic oxidation.
Also, another object of the present invention is to provide a method of manufacturing a semiconductor device which is excellent in yield and high in reliability by preventing the diffusion of aluminum from the wiring and the deformation of the wiring which are caused by heating.
Hereinafter, a process through which the present invention has been achieved will be described with reference to FIGS. 43A to 48D.
(1. Anodic Oxidation)
The present inventors have recognized whether an island-like aluminum pattern can be anodically oxidized on a tantalum film which is used as an electrode, or not. FIGS. 43A to 43E are cross-sectional views showing an aluminum pattern in the respective experimental procedures. In this example, aluminum is anodically oxidized by oxalic acid or tartaric acid as in the conventional example.
(Experimental Procedure)
A tantalum (Ta) film 41 having a thickness of 20 nm and an aluminum (Al) film 42 having a thickness of 400 nm are laminated on a 1737 glass substrate (5 inch square) 40 made by Corning Corp. In the gate wirings of the present invention, the Ta film 41 corresponds to a first conductive film, and the Al film 42 corresponds to a second conductive film. Then, a probe of an anodic oxidation device is connected to the aluminum film 42 and the surface of the aluminum film is anodically oxidized to form a barrier type anodic oxide film 44. Also, the barrier type anodic oxide film (hereinafter referred to as xe2x80x9cbarrier A.O. filmxe2x80x9d) is made of alumina (FIG. 43A).
The anodic oxidation conditions are that ethylene glycol solution containing tartaric acid of 3% is used as an electrolyte solution, a solution temperature is 30xc2x0 C., an arrival voltage is 10 V, a voltage supply period of time is 15 minutes, and a supply current is 10 mA/substrate. The anodic oxidation process is made in order to improve the adhesion of the resist mask 50. Since the barrier A.O. film 44 is formed on the surface of the Al film 42, the anodic oxidation process is called xe2x80x9cmask anodic oxidation processxe2x80x9d in the present specification. The alumina film 44 which has been anodically oxidized by tartaric acid has the corrosiveness with respect to bufferred hydrofluoric acid.
Subsequently, a resist mask 50 is formed on the upper surface, and the A.O. film 44 and the Al film 42 are etched to form a plurality of gate wiring patterns 43 formed of the Al film 42 (hereinafter referred to as xe2x80x9cAl pattern 43xe2x80x9d). The Al patterns 43 are separately formed for each of the wirings, and only two Al patterns 43 are shown in FIGS. 43B to 43E. The Al patterns 43 correspond to a second wiring layer of the present invention.
The etchant of the barrier A.O. film 44 as used is an acid in which a chromic acid solution 550 g (chromic acid 300 g, water 250 g) is mixed with a solution 10 litters mixed with phosphoric acid, nitric acid, acetic acid and water at a rate of 85:5:5:5. In the present specification, the above-mentioned etchant is called xe2x80x9cchromic mixed acidxe2x80x9d. The etchant of the Al film 42 as used is an acid in which phosphoric acid, acetic acid, nitric acid and water are mixed at a rate of 85:5:5:5 by volume % (hereinafter referred to as xe2x80x9caluminum mixed acidxe2x80x9d) (FIG. 43B).
Then, a voltage is applied to the Ta film 41 in an anodic oxidation device while the resist mask 50 remains to conduct anodic oxidation. The conditions are that oxalic acid aqueous solution of 3% is used as an electrolyte solution, an arrival voltage is 8 V, a voltage supply period of time is 40 minutes, and a supply current is 20 mA/substrate. In the conventional anodic oxidation method, with these anodic oxidation conditions, a porous type anodic oxide (porous A.O.) film 45 is formed on the side surface of the aluminum patter 43. Thus, this anodic oxidation process is called xe2x80x9cside anodic oxidation processxe2x80x9d in the present specification (FIG. 43C). Then, after the removal of the resist mask 50, a voltage is applied to the Ta film 41 again in the anodic oxidation device to conduct anodic oxidation. The conditions are that ethylene glycol solution containing tartaric acid of 3% is used as an electrolyte solution, an electrolyte solution temperature is 10xc2x0 C., an arrival voltage is 80 V, a voltage supply period of time is 30 minutes, and a supply current is 30 mA/substrate. In the conventional method, in these anodic oxidation conditions, tartaric acid permeates the porous A.O. film 45, and the surface of the Al pattern 43 is anodically oxidized to form a barrier type anodic oxide (barrier A.O.) film 46. Accordingly, this anodic oxidation process is called xe2x80x9cbarrier anodic oxidation processxe2x80x9d in the present specification. The barrier A.O. film 46 is made of non-porous alumina and have a hydrofluoric acid resistance (FIG. 43D).
Then, the porous A.O. film 45 is removed by wet etching using the above-described aluminum mixed acid. The barrier A.O. film 46 is hardly etched by aluminum mixed acid (FIG. 43E).
(Experimental Results and Consideration)
In order to recognize whether the Ta film 41 functions as the voltage supply wiring for anodic oxidation of the Al pattern, or not, the sheet resistance of the Ta film 41 has been measured for each of the processes.
Also, the cross-sectional structure of the Al pattern 43 has been observed through a transmission electron microscope (hereinafter referred to as xe2x80x9cTEMxe2x80x9d) in order to investigate the cross-sectional structure thereof. In addition, elements in the fine region of the sectional structure are analyzed by an electron dispersion X-ray spectroscopy (hereinafter referred to as xe2x80x9cEDXxe2x80x9d). FIGS. 44A and 44B are photographs of the section of the Al pattern 43 shown in FIG. 43E which has been observed through the TEM, and FIG. 44C is a schematic diagram of the photographs of that section observed through the TEM. The TEM photograph of FIG. 44B shows an enlargement of the lower structure of the porous A.O. film 45. Also, the reference numerals used in FIG. 44C are identical with those in FIGS. 43A to 43E.
The sheet resistance of the Ta film 41 is 100.1 xcexa9/square cm in an initial state (before mask anodic oxidation), and 205.1 xcexa9/square cm after the side anodic oxidation process has been finished. The sheet resistance after the barrier anodic oxidation process has been finished becomes equal to or higher than a measurable range of a measuring device. Since the maximum measurable value of the measuring device is 5000 kxcexa9/square cm, it is presumed that the sheet resistance after the barrier anodic oxidation process has been finished is at least 5000 kxcexa9/square cm or higher.
As a result of observing the glass substrate 40 by eyes after the side anodic oxidation process has been finished, the Ta film 41 becomes slightly more transparent than that in the initial state. It is presumed from the observation by eyes and the sheet resistance that the surface of the Ta film 41 is slightly oxidized through the side anodic oxidation process to form a tantalum oxide film (hereinafter referred to as xe2x80x9cTaOx filmxe2x80x9d) 51. This presumption is also supported by the TEM observation and the EDX analysis result which will be described later.
Further, upon observation of the glass substrate 40 by eyes after the barrier anodic oxidation process has been completed, the Ta film 41 which has been exposed becomes almost transparent. This is because tartaric acid used during the mask anodic oxidation process also anodically oxidizes tantalum, and it is presumed that the Ta film 41 of that portion is anodically oxidized over the entire thickness of the film so as to be converted into a TaOx film 52. This presumption is also supported by the TEM observation and the EDX analysis result which will be described later.
However, because tantalum oxide is of an insulator, there arises a problem as to whether the TaOx films 51 and 52 function as a wiring, or not. Since there is found no large fluctuation in a current value monitored by an anodic oxidization device during the barrier anodic oxidization process, it is presumed that even if the Ta film 41 is converted into the TaOx film, a voltage is applied to the Al pattern 43. It is presumed that this exhibits a slight conductivity (semi-insulation) because the TaOx film is very large in sheet resistance but has the content of oxygen smaller than Ta2O5 (tantalum pentoxide) which is stoichiometric ratio. It is presumed that the shift from the stoichiometric ratio is largely caused by that the TaOx films 51 and 52 are formed by anodic oxidation.
In the etching process shown in FIG. 43E, aluminum mixed acid is employed. Although both of porous alumina (porous A.O. film 45) and aluminum (Al pattern 43) are etched by aluminum mixed acid, non-porous alumina (barrier A.O. film 46) is hardly etched. Accordingly, if the barrier A.O. film 46 is formed with a sufficient thickness in the barrier anodic oxidation process, the Al pattern 43 should not be etched.
It can be recognized from the TEM observation photograph of FIG. 44A that the Al pattern 43 remains even if the etching process is conducted with aluminum mixed acid. Accordingly, it can be presumed that the barrier A.O. film 46 that can withstand aluminum mixed acid is formed in the mask anodic oxidation process. According to the TEM observation photographs shown in FIGS. 44A and 44B, the thickness of the barrier A.O. film 46 is about 20 nm.
It has been found out through the above-mentioned experiments that the Al pattern 43 selectively formed on the upper portion of the Ta film 41 formed on the entire surface of the glass substrate 40 is short-circuited by the Ta film 41, and a voltage is applied to the Ta film 41, thereby making it possible to anodically oxidize the Al pattern 43. In particular, it has been recognized that even if the Ta film 41 is used for the voltage supply wiring in the anodic oxidation process using tartaric acid, the Al pattern 43 formed on the upper portion of the Ta film 41 can be anodically oxidized.
Hereinafter, the TaOx films 51 and 52 will be considered on the basis of the TEM observation photograph and the EDX analysis result.
It is found from the TEM observation photographs shown in FIGS. 44A and 44B that three different layers 51, 52a and 52b (refer to FIG. 44B) exist in the TaOx film. The composition of the respective layers of 51, 52a and 52b has been analyzed by the EDX. In FIG. 44B, points P1 to P6 indicated by xe2x80x9c*xe2x80x9d designate measurement points of the EDX.
The measurement point P1 is a portion which is not immersed in an electrolyte solution during all of the anodic oxidation processes and serves as a reference point for other measurement points. Although most of peaks at the measurement point P1 are Ta, low peaks such as C or O have also been recognized.
The measurement points P2 and P3 are portions which are immersed in the electrolyte solution during the porous anodic oxidation process and the barrier anodic oxidation process. At the measurement points P2 and P3, the measurement results of EDX are nearly identical with each other, in which the peaks of Ta and O are detected. Since the peak of O is higher than that at the point P1, it is presumed that Ta is anodically oxidized and converted into tantalum oxide (hereinafter referred to as TaOx) at the measurement points P2 and P3.
However, in the TEM photograph, since the TaOx film 51 which is a lower layer (measurement point P2) and the TaOx film 52b which is an upper layer (measurement point P3) are different in contrast from each other, it is presumed that the crystal structure is different between the TaOx film 52b and TaOx film 51. The TaOx film 51 is a portion which has been oxidized during the side anodic oxidation process of FIG. 43C, and it is presumed that the TaOx film 51 is of the porous crystal structure. The TaOx film 52b which is the lower layer is a portion which has been oxidized during the barrier anodic oxidation process, and it is presumed that the TaOx film 52b is finer in crystal structure than the TaOx film 51 which is the upper layer.
Since in the region where the porous A.O. film 45 exists, the detected peak of elements at the measurement point P4 in the vicinity of the boundary of the glass substrate 40 is nearly identical with that at the measurement point P1, it is presumed that Ta is not anodically oxidized at that portion and remains as the Ta layer 40.
At the measure point P5, the peaks of Ta, O and Al are detected. The peak of O is higher than that at the point P1. It is presumed that TaOx and Al exist together in the TaOx film 52a, or the alloy of Ta and Al is oxidized. In the TEM photograph, it is found that the TaOx film 52a is shaped in needles (porous shaped) or shaped in a cotton, and it is presumed that the TaOx film 52a is the lowest density in the TaOx film.
Since the EDX result at the measurement point P6 between the measurement points P4 and P5 is nearly identical with that at the measurement point P3, it is presumed that the TaOx film 52b is TaOx which has been oxidized during the barrier anodic oxidation process.
It is presumed from the above-mentioned TEM observation photograph and the EDX that the TaOx layers 51 and 52b different in density (contrast on the photograph) are formed on the glass substrate 40 in the region outside of the porous A.O. film 45.
On the other hand, it is presumed that in the region under the porous A.O. film 45, three-layer films consisting of the Ta film 41, the TaOx film 52a and the TaOx film 52b are formed on the glass substrate 40, and the TaOx film 52b is TaOx containing Al therein or the oxide of an alloy consisting of Al and Ta.
The present invention has been based on the above-described experimental results, and has one structure in which in order to anodically oxidize a wiring formed of an Al layer, a Ta film is formed over the entire surface of the substrate as the lower layer of the Al layer, and the Ta film is used as a voltage supply line.
Therefore, the gate wiring of a two-layer structure consisting of Al and Ta shown in FIGS. 43A to 43E is applied to the gate wiring of the TFT shown in FIGS. 49A to 49F to thus produce a TFT. However, there arises the following problems.
In the conventional example, in order to form the LDD in a self-aligning manner, the gate insulating film 14 is etched with the porous A.O. film 17 as a mask (refer to FIG. 49D). The gate insulating film 14 is made of nitrified silicon oxide or silicon oxide. A dry etching process using CHF3 gas is used for etching the gate insulating film 14.
After the gate insulating film 14 has been etched, the porous A.O. film 17 is wet-etched by aluminum mixed acid (refer to FIG. 49E), and at this time, etching remainder frequently occurs. Therefore, after wet-etching, the remainder is removed by a chemical only for remainder etching. It is proved that the remainder is a reaction product stuck to the side surface of the porous A.O. film 17 by dry-etching the gate insulating film 14.
If the wiring having the two-layer structure consisting of Al and Ta shown in FIGS. 43A to 43E is applied to the conventional TFT manufacturing process shown in FIGS. 49A to 49F, the TaOx film is dry-etched together with the gate insulating film during the dry etching process of the gate insulating film shown in FIG. 49D, and a reaction product is similarly stuck to the side surface of the porous alumina film in this dry etching process.
Likewise, in this case, although the film is processed by a chemical only for remainder etching as described above after the porous alumina film has been wet-etched, the remainder can be hardly removed. Even after the film has been processed by the chemical, the remainder exists in a state where a wall-like structure erects just around the periphery of the porous A.O. film 17, or in a state where the wall-like structure is turned upside down, and the base of the wall-like remainder is firmly fitted to the substrate. It is presumed that the reason why the wall-like remainder can not be removed from the substrate even if it is processed by the remainder removal chemical is that metal components such as Ta is mixed with the reaction product obtained when the gate insulating film is dry-etched.
In order to eliminate the problem of the remainder occurrence, the present invention has another structure in which the gate insulating film and the TaOx film are not dry-etched at the same time with the porous alumina as a mask when the gate wiring of the two-layer structure consisting of Al and Ta is used.
Also, in the conventional example, portions where lightly-doped impurity regions 23 and 24 exist under the gate insulating film 14xe2x80x2 are portions where the porous A.O. film 17 has existed. Accordingly, in the case where the wiring of the two-layer structure consisting of Al and Ta shown in FIGS. 43A to 43E is applied to the gate wiring of the TFT shown in FIGS. 49A to 49F, the Ta film 41 exists on the lightly-doped impurity regions 23 and 24 through the gate insulating film 14xe2x80x2 according to the above-described EDX analysis result. This structure causes a voltage to be always applied to the lightly-doped impurity regions 23 and 24 by the Ta film 41 in the on-state, resulting in such a problem that the deterioration of the TFT is hastened.
The remainder of the Ta film on the lightly-doped impurity region is caused by anodically oxidizing the Ta film 41 in a state where the Ta film 41 is coated with the porous A.O. film 45. Since the electrolyte solution does not sufficiently go over a portion coated with the porous A.O. film 45, the Ta film 41 cannot be anodically oxidized over the entire thickness of the film. Accordingly, an object of the present invention is to eliminate the remaining Ta film on the lightly-doped impurities. In order to achieve this object, the present invention has another structure in which a barrier anodic oxidation process is conducted without conducting the side anodic oxidation process shown in FIG. 43C to anodically oxidize the Ta film (first conductive film) and the Al pattern (second wiring layer) 43.
In other words, in the present invention, in the formation of the respective anodic oxide films that coat the first wiring layer and the second wiring layer, the surface of a portion of the first conductive film to be anodically oxidized is exposed so that the first conductive film is surely anodically oxidized.
Also, the present invention has a process of thermally oxidizing the Ta film in order to eliminate the Ta film which has remained during the side anodic oxidation process shown in FIG. 43C. That is, the present invention has another structure in which there is provided a process of thermally oxidizing the first conductive film after the first conductive film has been anodically oxidized.
(2. Evaluation of the blocking property of Ta layer)
Subsequently, the blocking property of the Al diffusion in the Ta layer will be evaluated. A sample in which a Ta layer is formed (called xe2x80x9csample Axe2x80x9d) and a sample in which no Ta layer is formed (called xe2x80x9csample Bxe2x80x9d) are subjected to a heat treatment in a nitrogen atmosphere, and the distributions of the Al concentrations of the respective samples after the heat treatment has been made have been measured through the secondary ion mass spectroscope (SIMS). The heat treatment was conducted at a temperature of 550xc2x0 C. for a processing period of 2 hours in the nitrogen atmosphere.
FIGS. 45A and 45B show cross-sectional structures of the respective samples A and B. The sample A is that a polycrystal silicon film 61 (200 nm in thickness) corresponding to a semiconductor layer, a nitrified silicon oxide (SiON) film 62 (120 nm) corresponding to a gate insulating film, a tantalum film 63 (20 nm) an aluminum film 64 (200 nm) which constitutes a gate wiring are laminated on a Corning 1737 glass substrate 60.
The sample B corresponds to the sample A from which the tantalum film 63 is removed, and is that a polycrystal silicon film 71 (200 nm in thickness) corresponding to a semiconductor layer, a nitrified silicon oxide (SiON) film 72 (120 nm) corresponding to a gate insulating film and an aluminum (Al) film 74 (200 nm) are laminated on a Corning 1737 glass substrate 70.
An SIMS measuring direction is directed from the glass substrates 60 and 70 toward the aluminum films 64 and 74 with respect to both of the samples A and B. The analyzing conditions are identical between the samples A and B and are that a primary ion species is O2+, a primary acceleration voltage is 6.0 kV, a sputtering rate is 0.6 nm/s, a measured region is 120 xcexcmxc3x97192 xcexcm, and the degree of vacuum is 3xc3x9710xe2x88x927 Pa. The elements to be analyzed are Al, O, Si and Ta.
The SIMS analyzing results of the samples A and B are shown in FIGS. 46 and 47. In FIGS. 46 and 47, the axis of abscissa is the depth [xcexcm], the left axis of ordinate is the concentration of Al [atoms/cm3] and the right axis of ordinate is a secondary ion intensity [cts/sec] of O, Si and Ta.
In quantifying the concentration of Al, an SiO2 normal sample into which Al ions have been implanted and an Si normal sample into which Al ions have been implanted are used as normal samples. The profiles of the concentrations of Al shown in FIGS. 46 and 47 are processing data. There are shown a profile quantified using the SiO2 normal sample in the SiON films 62 and 72, and a profile quantified using the Si normal sample in the polycrystal silicon films 61 and 71. In FIGS. 46 and 47, the profile quantified using the SiO2 normal sample and the profile quantified using the Si normal sample are connected to each other. For that reason, the inaccuracy due to the data processing remains in the profile on the interface between the SiON film and Si film. The background level of the concentration of Al is 1xc3x971016 atoms/cm3 in the SiO2 normal sample and 1xc3x971015 atoms/cm3 in the Si normal sample.
As apparent from the comparison of FIG. 46 with FIG. 47, it is found that the Ta film 63 functions as a blocking film for preventing Al from diffusing. In the sample B (including no Ta layer), the concentration of Al is about 1xc3x971019 atoms/cm3 both in the Si film (semiconductor layer) 71 and in the SiON film (gate insulating film) 72. On the other hand, in the sample A (including a Ta layer), the concentration of Al is 3xc3x971016 atoms/cm3 or less in the SiON film 63, and the lowest concentration is about 1xc3x971016 atoms/cm3 or less of the background level. Also, the concentration of Al is within a range of from 1xc3x971015 atoms/cm3 to 1xc3x971017 atoms/cm3 in the Si film 61.
FIGS. 48A to 48D show the optical microscope photographs of the samples A and B which have been subjected to a heat treatment at 550xc2x0 C., respectively. FIG. 48A shows the sample B and FIG. 48B shows the sample A. Also, FIGS. 48C and 48D show the sample A in which the thickness of the Ta layer 63 is set at 30 nm and 50 nm, respectively.
In FIG. 48A, in case of the single Al layer (Ta layer=0 nm), it is recognized that aluminum diffuses (oozes). On the other hand, it can be understood from FIGS. 48B to 48D that the formation of the Ta layer having a thickness of 20 nm or more under the aluminum layer can prevent aluminum from oozing.
As described above, it is understood that the gate wiring with the two-layer structure consisting of the Al layer and the Ta layer can prevent Al from diffusing into the semiconductor layer or the gate wiring. According to the present inventors"" knowledge, in order to obtain the Al blocking effect, it is necessary to provide the Ta layer of 1 nm or more, preferably, 5 nm or more in thickness. In the case where the thickness of the Ta layer is less than 1 nm, it is difficult to form a film having no pin holes because of the performance of the film forming device, thereby disenabling the blocking effect to be expected.
Also, it is considered that the upper limit of the Ta layer is about 400 nm, preferably, about 200 nm. In the case where it is more than about 400 nm, the aluminum material layer must be thinned in order to suppress the thickness of the gate electrode, thereby disenabling the feature of aluminum, that is, the low resistivity of aluminum to be made the best use of.
From the above-mentioned viewpoints, the thickness of the tantalum layer is set at 1 to 50 nm, preferably 1 to 20 nm, more preferably 5 to 20 nm.
Also, because the degree to which aluminum diffuses becomes larger as a temperature at which a heat treatment is conducted on the gate wiring is high, the thickness of the Ta layer may be set according to the heating temperature. For example, the thickness of the Ta layer is determined in such a manner that the lowest value of the concentration of Al within an under insulating film of the Ta layer (the SiON film 62 in case of FIGS. 45A and 45B) becomes 3xc3x971016 atoms/cm3 or less, more preferably 1xc3x971016 atoms/cm3 or less, or in such a manner that the lowest value of the concentration of Al within the semiconductor layer becomes 1xc3x971017 atoms/cm3 or less, more preferably 1xc3x971016 atoms/cm3 or less.
The aspects of the present invention are based on the knowledge obtained from the above-mentioned experimental results. In order to achieve the above-mentioned objects, according to a first aspect of the present invention, there is provided a semiconductor device having a gate wiring which intersects with a semiconductor layer through a gate insulating film, said gate wiring comprising:
a first wiring layer made of a first conductive film formed in contact with the gate insulating film;
a second wiring layer made of a second conductive film formed in contact with an upper surface of the first wiring layer;
an anodic oxide film of the first conductive film which is in contact with a side surface of the first wiring layer; and
an anodic oxide film of the second conductive film which is in contact with a front surface of the second wiring layer,
wherein the upper surface of the gate insulating film is coated with the anodic oxide film of the first conductive film except for a portion where the first wiring layer is formed.
Also, according to a second aspect of the present invention, there is provided a semiconductor device having a gate wiring which intersects with a semiconductor layer through a gate insulating film, the gate wiring comprising:
a first wiring layer made of a first conductive film formed in contact with the gate insulating film;
a second wiring layer made of a second conductive film formed in contact with an upper surface of the first wiring layer;
an anodic oxide film of the first conductive film which is in contact with a side surface of the first wiring layer; and
an anodic oxide film of the second conductive film which is in contact with a front surface of the second wiring layer,
wherein the gate insulating film covers the entire surface of the semiconductor layer, and the anodic oxide film of the first conductive film is not formed on the surface of a region which covers at least the source region and the drain region.
According to the present invention, the gate wiring uses the second wiring layer which is an upper layer mainly as a charge passage. The thickness of the second wiring layer is set at about 200 to 500 nm. Also, it is preferable that the metal film that forms the second wiring layer is made of aluminum or a material mainly containing aluminum in order to obtain the low resistance of the wiring.
Also, the first conductive film may be made of valve metal. The valve metal is directed to a metal which exhibits that a barrier type anodic oxide film anodically produced allows a cathode current to flow therein but does not allow an anode current to flow therein, that is, exhibits a valve action (see xe2x80x9cElectrochemical Handbookxe2x80x9d, Fourth Edition; xe2x80x9cElectrochemical Association Journalxe2x80x9d, p 370, Maruzen, 1985).
In order to obtain the Al blocking effect, a valve metal film a material of which has a melting point higher than that of aluminum is used for the first conductive film . The metal of this type may be tantalum (Ta), niobium (Nb), hafnium (Hf), zirconium (Zr), titanium (Ti), chromium (Cr) or the like. Also, the first conductive film can be made of an eutectic alloy consisting of any one of those valve metal elements and other metal elements or nitrogen. For example, a molybdenum tantalum (MoTa) alloy, or a nitrogen alloy such as TaNy, NbNy, HfNy, ZrNy, TiNy or CrNy may be employed.
Although it is preferable that the thickness of the first conductive film is thinner, the thickness for functioning as a blocking layer that prevents the structural atoms of the second wiring layer from diffusing is required. The lower limit of the first conductive film is set at 1 nm, preferably 5 nm.
The primary reason why the thinner first conductive film is desired is that in formation of source and drain regions, impurities are added to the semiconductor layer after passing through the first anodic oxide film, that is, the anodic oxide film of the first conductive film. As the anodic oxide film is thinner, an accelerating voltage during the impurity adding process and the dose amount can be decreased, to thereby improving a throughput. Also, the throughput during the process of forming the first conductive film and during the process of etching the anodic oxide of the first conductive film can be more heightened as the first conductive film is thinner.
Also, the upper limit of the thickness of the first conductive film is set at 50 nm, preferably about 30 nm. The first oxide film is formed by oxidizing the first conductive film so that the thickness thereof is about 2 to 4 times as large as that of the first conductive film. Accordingly, taking into account the formation of the first conductive film, the throughput during the processes of etching the anodic oxide film in the first aspect of the present invention and the first anodic oxide film in the second aspect of the present invention, and during adding the impurities etc., the upper limit of the first conductive film is set at 50 nm, preferably 30 nm.
It is considered from the above-mentioned viewpoints that the thickness of the first conductive film is preferably selected from a range of 1 to 50 nm (preferably 5 to 30 nm, more preferably 5 to 20 nm).
Also, because the degree to which aluminum diffuses becomes larger as a temperature at which a heat treatment is conducted on the gate wiring is high, the thickness of the first wiring layer may be set according to the heating temperature. For example, the thickness of the first wiring layer may be determined in such a manner that the lowest value of the concentration of Al within an under insulating film of the first wiring layer (the SiON film 62 in the case of FIGS. 45A and 45B) becomes 3xc3x971016 atoms/cm3 or less, more preferably 1xc3x971016 atoms/cm3 or less, or in such a manner that the lowest value of the concentration of Al within the semiconductor layer becomes 1xc3x971017 atoms/cm3 or less, more preferably 1xc3x971016 atoms/cm3 or less. The concentration of Al is defined with the lowest value of SIMS data.
In the structure according to the second aspect of the present invention, the anodic oxide film of the first conductive film and the gate insulating film are prevented from being etched at the same time, and only the anodic oxide film of the first conductive film is patterned to selectively expose the surface of the gate insulating film. A region of the gate insulating film the surface of which is exposed is a region that covers the source and drain regions. With this structure, the through-put is improved more than that in a case where impurities are added through both of the anodic oxide film of the first conductive film and the gate insulating film during the process of forming the source and drain regions.
It should be noted that in the present specification, an intersecting portion of the semiconductor layer and a connecting portion of another wiring with respect to the wirings such as the gate wiring, the source wiring or the drain wiring are particularly called xe2x80x9celectrodexe2x80x9d.